HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 37

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Item
15.3.3 Multiprocessor
Communication
Function
Figure 15.16 Example
of SCI Receive
Operation (Example with
8-Bit Data,
Multiprocessor Bit, One
Stop Bit)
15.5 Usage Notes
Handling of TEND Flag
and TE Bit
17.1 Overview
17.2.3 Serial Control
Register (SCSCR1)
17.2.4 Serial Status
Register (SCSSR1)
19.1.2 Block Diagram
Figure 19.1 Block
Diagram of INTC
Page
652
667, 668 Description added
719
724
726
770
Revision (See Manual for Details)
Figure replaced
To send a break signal during serial transmission, clear the
SPB0DT bit to 0 (designating low level), then clear the TE bit to
0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of its current state, and the
TxD pin becomes an output port outputting the value 0.
Handling of TEND Flag and TE Bit: The TEND flag is set to 1
when the stop bit of the final data segment is transmitted. If the
TE bit is cleared immediately after confirming that the TEND
flag was set, transmission may not complete properly because
stop bit transmission processing is still underway. Therefore,
wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits
are used) after confirming that the TEND flag was set before
clearing the TE bit.
Description amended
The serial communication interface (SCI) supports a subset of
the ISO/IEC 7816-3 (identification cards) standard as an
extended function.
Description added
Bits 3 and 2—Reserved:
Description added
Bits 1 and 0—Reserved:
Figure amended
Interrupt
request
IMASK
SR
CPU
Rev.4.00 Oct. 10, 2008 Page xxxv of xcviii
REJ09B0370-0400

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