HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 998

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. PCI Controller (PCIC)
Bits 31 to 0—Address Log (ALOG31 to 0): PIC address data (value of A/D line) at time of error.
(Initial value is undefined.)
22.2.23 PCI Command Data Register at Error (PCICLR)
The PCI command data register at error (PCICLR) stores the type of transfer (MSTPIO,
MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, or TGT) when an error occurs on the PCI
bus, and the PCI command (CMDLOG [3:0]). It is a 32-bit register that can be read from both the
PP bus and PCI bus.
Although bits 31 to 26 of the PCICLR register are initialized at a power-on reset and a software
reset, bits 3 through 0 are not initialized. When an error is detected, 1 is set in one of bits 31 to 26,
and the relevant command value is retained in bits 3 to 0.
Rev.4.00 Oct. 10, 2008 Page 898 of 1122
REJ09B0370-0400
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
Initial value:
Initial value:
Initial value:
Initial value:
PCI-R/W:
PCI-R/W:
PCI-R/W:
PCI-R/W:
Bit:
Bit:
Bit:
Bit:
MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3
31
23
15
—
—
—
R
R
R
R
R
R
R
R
0
0
0
7
0
30
22
14
—
—
—
R
R
R
R
R
R
R
R
0
0
0
6
0
29
21
13
—
—
—
R
R
R
R
R
R
R
R
0
0
0
5
0
28
20
12
—
—
—
R
R
R
R
R
R
R
R
0
0
0
4
0
CMDLOG3 CMDLOG2 CMDLOG1 CMDLOG0
27
19
11
—
—
—
R
R
R
R
R
R
R
R
0
0
0
3
TGT
26
18
10
—
—
—
R
R
R
R
R
R
R
R
0
0
0
2
25
17
—
—
—
—
R
R
R
R
R
R
R
R
0
0
9
0
1
24
16
—
—
—
—
R
R
R
R
R
R
R
R
0
0
8
0
0