HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 288

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6. Floating-Point Unit
Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input
data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001,
the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and
FPSCR.Cause.I should be set to 1. However, the result actually produced by the FPU is DR2 =
H'C4B250D2 0CC1F974, and FPSCR.Flag.I and FPSCR.Cause.I are not set to 1.
Effects: In addition to the problem described above, the numerical size of the result of the
operation may contain a minute operation error equivalent to 1/256 of the LSB of the mantissa of
the unrounded value. This is can be described as within the scope of the subsequent rounding
mechanism. Strictly speaking, it consists of the following.
a: The infinite-precision operation result
b: The closest expressible value less than a
c: The closest expressible value greater than a
d: The operation result when a is rounded correctly
e: The operation result when a is rounded by the FPU
• The rounding error when rounding is performed correctly in Round to Nearest mode is:
• The rounding error when rounding is performed correctly in Round to Zero mode is:
And the rounding error when rounding is performed by the FPU is:
Rev.4.00 Oct. 10, 2008 Page 188 of 1122
REJ09B0370-0400
0 ≤ | d − a | ≤ (1/2) × (c − b)
And the rounding error when rounding is performed by the FPU is:
0 ≤ | e − a | < (129/256) × (c − b)
If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to
1/256 of the LSB of the mantissa of the correctly rounded value.
(−1) × (c − b) < | d |−| a | ≤ 0
(−1) × (c − b) < | e |−| a | < (1/256) × (c − b)
If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to
1/256 of the LSB of the mantissa of the correctly rounded value.