HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 170

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. Memory Management Unit (MMU)
• URB: Bits that indicate the UTLB entry boundary at which replacement is to be performed.
• URC: Random counter for indicating the UTLB entry for which replacement is to be
• SQMD: Store queue mode bit. Specifies the right of access to the store queues.
• SV: Bit that switches between single virtual memory mode and multiple virtual memory mode.
• TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB
• AT: Address translation enable bit. Specifies MMU enabling or disabling.
Rev.4.00 Oct. 10, 2008 Page 70 of 1122
REJ09B0370-0400
Ensure that values for which “Setting prohibited” is indicated in the above table are not set at
the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,
and therefore a prohibited setting is never made by a hardware update.
Valid only when URB > 0.
performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed.
When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a
value is written to URC by software which results in the condition URC > URB, incrementing
is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB
instruction.
0: User/privileged access possible
1: Privileged access possible (address error exception in case of user access)
0: Multiple virtual memory mode
1: Single virtual memory mode
When this bit is changed, ensure that 1 is also written to the TI bit.
bits. This bit always returns 0 when read.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is 0. In the case of software that does not
use the MMU, therefore, the AT bit should be cleared to 0.