HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 597

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.1
The SH7751 includes an on-chip four-channel direct memory access controller (DMAC). The
SH7751R has an on-chip eight-channel DMAC. The DMAC can be used in place of the CPU to
perform high-speed data transfers among external devices equipped with DACK (DMA transfer
end notification), external memories, memory-mapped external devices, and on-chip peripheral
modules (TMU, RTC, SCI, SCIF, CPG, and INTC). Using the DMAC reduces the burden on the
CPU and increases the operating efficiency of the chip. When using the SH7751R, see section
14.6, Configuration of the DMAC (SH7751R), section 14.7, Register Descriptions (SH7751R),
and section 14.8, Operation (SH7751R).
14.1.1
The DMAC has the following features.
• Four channels (SH7751), eight channels (SH7751R)
• Physical address space
• Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum of 16 M (16,777,216) transfers
• Choice of single or dual address mode
• Choice of bus mode: cycle steal mode or burst mode
• Two types of DMAC channel priority ranking:
• An interrupt request can be sent to the CPU on completion of the specified number of
⎯ Single address mode: Either the transfer source or the transfer destination (external device)
⎯ Dual address mode: Both the transfer source and transfer destination are accessed by
⎯ Fixed priority mode: Channel priorities are permanently fixed.
⎯ Round robin mode: Sets the lowest priority for the channel that last received an execution
transfers.
Section 14 Direct Memory Access Controller (DMAC)
is accessed by a DACK signal while the other is accessed by address. One data transfer is
completed in one bus cycle.
address. Values set in DMAC internal registers indicate the accessed address for both the
transfer source and the transfer destination. Two bus cycles are required for one data
transfer.
request.
Overview
Features
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 497 of 1122
REJ09B0370-0400