HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 438

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
13.1.3
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Address bus
Data bus
Bus cycle start
Chip select 6–0
Read/write
Row address
strobe
Read/column
address strobe/
cycle frame
Data enable 0
Data enable 1
Data enable 2
Data enable 3
Rev.4.00 Oct. 10, 2008 Page 338 of 1122
REJ09B0370-0400
Pin Configuration
Signals
A25–A0
D31–D0
BS
CS6–CS0
RD/WR
RAS
RD/CASS/
FRAME
WE0/REG
WE1
WE2/ICIORD
WE3/ICIOWR
I/O
O
I/O
O
O
O
O
O
O
O
O
O
Address output
Data input/output
Signal that indicates the start of a bus cycle
Chip select signals that indicate the area being
Data bus input/output direction designation signal
Strobe signal that indicates a read cycle
When setting PCMCIA interface: REG signal
When setting PCMCIA interface: write strobe signal
When setting PCMCIA interface: ICIORD signal
When setting PCMCIA interface: ICIOWR signal
Description
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
RAS signal when setting DRAM/synchronous DRAM
interface
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal
When setting SRAM interface: write strobe signal for
D7–D0
When setting SRAM interface: write strobe signal for
D15–D8
When setting SRAM interface: write strobe signal for
D23–D16
When setting SRAM interface: write strobe signal for
D31–D24