HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 657

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• 11: Channel 3
Bits 25 and 24: Transfer Request Mode (MD1, MD0)
• 00: Handshake protocol (data bus used)
• 01: Setting prohibited
• 10: Request queue clear specification
• 11: Setting prohibited
Bits 23 to 0: Reserved
Notes: 1. In channels 1 to 3, only the ID field is valid.
Usable SZ, ID, and MD Combination in DDT Mode
Table 14.11 shows the usable combination of SZ, ID, and MD in DDT mode of this LSI.
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode
SZ [2:0]
000
110
111
X
X
X
Legend: X: Don't care
Note: Don't set values other than those shown in the above table.
2. In channel 0, the MD field is valid. Set MD = 00. If 01, 10, or 11 is set, the DMAC
3. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst
4. When specifying data transfer requests using a handshake protocol for channel 0, set
will halt with an address error.
mode and cycle steal mode, a handshake protocol is used to transfer each unit of data.
DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101, 110 for the DTR format. Use the
MOV instruction to make settings in the DMAC's SAR0, DAR0, CHCR0, and
DMATCR0 registers. Either single address mode or dual address mode can be used as
the transfer mode.
Select one of the following settings: CHCR0.RS3—RS0 = 0000, 0010, 0011.
Operation is not guaranteed if the DTR format data settings are DTR.ID = 00,
DTR.MD = 00, and DTR.SZ ≠ 101, 110.
ID [1:0]
00
00
00
01
10
11
MD [1:0]
00
10
00
X
X
X
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 557 of 1122
Function
Request for transfer to channel 0
Request queue clear
Transfer end
Request for transfer to channel 1
Request for transfer to channel 2
Request for transfer to channel 3
REJ09B0370-0400