HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 225

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.6
To enable the IC and OC to be managed by software, IC contents can be read and written by a P2
area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is
made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be
made at least 8 instructions after this MOV instruction. The OC contents can be read and written
by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not
guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0,
or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are
allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC
address array and data array and the OC address array and data array, and the access size is always
longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value
of 0 should be specified, and read values are undefined. Note that the memory-mapped cache
configuration in SH7751-compatible-mode of the SH7751R is the same as that in the SH7751.
4.6.1
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is
specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry
specification. Address field bit [3], that is the association bit (A bit), specifies whether or not
association is performed when writing to the IC address array. As only longword access is used, 0
should be specified for address field bits [1:0].
Legend:
L:
Address field
: Reserved bits (0 write value, undefined read value)
Data field
Longword specification bits
Memory-Mapped Cache Configuration (SH7751R)
IC Address Array
31
31
1 1 1 1 0 1 0 1
Figure 4.11 Memory-Mapped OC Data Array
24
23
Longword data
Rev.4.00 Oct. 10, 2008 Page 125 of 1122
14
13
Entry
REJ09B0370-0400
5 4
4. Caches
L
2 1 0
0