HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 528

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
Commands for synchronous DRAM are specified by RAS, CASS, RD/WR, and specific address
signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks
(PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ),
read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register
setting (MRS).
Byte specification is performed by DQM0 to DQM3. A read/write is performed for the byte for
which the corresponding DQM signal is low. When the bus width is 32 bits, in big-endian mode
DQM3 specifies an access to address 4n, and DQM0 specifies an access to address 4n + 3. In
little-endian mode, DQM3 specifies an access to address 4n + 3, and DQM0 specifies an access to
address 4n.
Figure 13.23 shows examples of the connection of 16M × 16-bit synchronous DRAMs.
Rev.4.00 Oct. 10, 2008 Page 428 of 1122
REJ09B0370-0400
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
SH7751/SH7751R
D31–D16
D15–D0
A11–A2
RD/WR
DQM3
DQM2
DQM1
DQM0
CASS
CKIO
CKE
RAS
CS3
512k × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML