HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 157

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)
Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
• FR: Floating-point register bank
• SZ: Transfer size mode
• PR: Precision mode
• DN: Denormalization mode
• Cause: FPU exception cause field
• Enable: FPU exception enable field
• Flag: FPU exception flag field
31
FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–
FPR15_BANK1 are assigned to XF0–XF15.
FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–
FPR15_BANK1 are assigned to FR0–FR15.
SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (the result of
instructions for which double-precision is not supported is undefined).
Do not set SZ and PR to 1 simultaneously; this setting is reserved.
[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
DN = 0: A denormalized number is treated as such.
DN = 1: A denormalized number is treated as zero.
Cause
Enable
Flag
FPU exception
FPU exception
cause field
enable field
FPU exception
flag field
—
22 21 20 19 18 17
FPU
Error (E)
Bit 17
None
None
FR SZ PR DN
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
Cause
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
Rev.4.00 Oct. 10, 2008 Page 57 of 1122
12 11
Overflow
(O)
Bit 14
Bit 9
Bit 4
Enable
2. Programming Model
7
Underflow
(U)
Bit 13
Bit 8
Bit 3
6
REJ09B0370-0400
Flag
Inexact
(I)
Bit 12
Bit 7
Bit 2
2
1
RM
0