HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 204

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4. Caches
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
• EMODE: Cache-double-mode bit
Note: 1. Address allocation in OC index mode and RAM mode is not compatible with that in
• IIX: IC index enable bit
• ICI: IC invalidation bit
• ICE: IC enable bit
• OIX: OC index enable bit*
Note: 2. In the SH7751R, clear the OIX bit to 0 when the ORA bit is 1.
• ORA: OC RAM enable bit*
Note: 3. In the SH7751R, clear the ORA bit to 0 when the OIX bit is 1.
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Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in the
SH7751. The EMODE bit cannot be modified while the cache is in use.
0: SH7751-compatible-mode*
1: Cache-double-mode
0: Effective address bits [12:5] used for IC entry selection
1: Effective address bits [25] and [11:5] used for IC entry selection
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
0: Effective address bits [13:5] used for OC entry selection
1: Effective address bits [25] and [12:5] used for OC entry selection
When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be
used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: Normal mode (the entire OC is used as a cache)
1: RAM mode (half of the OC is used as a cache and the other half is used as RAM)
RAM mode.
2
3
1
(Initial value)