HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 15

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
4.2 Register
Descriptions
•
4.3.1 Configuration
LRU (SH7751R only)
4.3.10 Notes on Using
OC RAM Mode
(SH7751R Only) when
in Cache Enhanced
Mode
4.4.1 Configuration
LRU (SH7751R only)
4.7 Store Queues
4.7.6 SQ Usage Notes
(SH7751R only)
ORA: OC RAM
enable bit*
3
Page
104
108
114 to
116
119
131, 132 Description added
134
Revision (See Manual for Details)
Description amended
When the OC is enabled (OCE = 1), the ORA bit specifies
whether the half of the OC are to be used as RAM. When the
OC is not enabled (OCE = 0), the ORA bit should be cleared to
0.
0: Normal mode (the entire OC is used as a cache)
1: RAM mode (half of the OC is used as a cache and the other
half is used as RAM)
Description deleted
In a 2-way set-associative system, up to two entry addresses
Newly added
Description deleted
In a 2-way set-associative system, up to two entry addresses
Note that power-down modes (STBCR2.MSTP6 = 1) that stop
SQ functions cannot be used on the SH7751 when using the
operand cache for write-back operations.*
Note:
Title amended
*
can register the same data in cache.
can register the same data in cache.
Cases where write-back operations are performed:
•
•
When the operand cache is used in copy-back
mode (determined by the CCR.CB and
CCR.WT bits and, if address translation is
performed, the WT bit in the page management
information)
When the memory allocation cache function is
used to write to the OC address array, and an
entry is generated when both the V and U bits
are set to 1
Rev.4.00 Oct. 10, 2008 Page xiii of xcviii
REJ09B0370-0400