HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 957

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 31 to 16—DEVID15 to 0: These bits specify the device ID of the SH7751 or SH7751R
allocated by the PCI device vendor. H'3505 (fixed in hardware) for the SH7751, and H'350E
(fixed in hardware) for the SH7751R.
Bits 15 to 0—DNVID15 to 0: These bits specify the PCI device maker (vendor ID). (H'1054*:
fixed in hardware)
Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but the SH7751 and SH7751R are now
22.2.2
Note: Cleared by writing WC: 1. (Writing of 0 is ignored.)
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
Initial value:
Initial value:
Initial value:
Initial value:
PCI-R/W:
PCI-R/W:
PCI-R/W:
PCI-R/W:
PCI Configuration Register 1 (PCICONF1)
Bit:
Bit:
Bit:
Bit:
products of Renesas Technology Corp. For information on these products, contact
Renesas Technology Corp.
R/WC
R/WC
FBBC
WCC
DPE
R/W
R/W
31
23
15
—
R
R
R
R
0
1
0
7
1
R/WC
R/WC
SSE
UDF
PER
R/W
R/W
R/W
30
22
14
—
R
R
R
0
0
0
6
0
R/WC
R/WC
RMA
66M
R/W
VPS
29
21
13
—
R
R
R
R
R
0
0
0
0
5
R/WC
R/WC
MWIE
RTA
PM
28
20
12
—
R
R
R
R
R
R
0
1
0
4
0
Rev.4.00 Oct. 10, 2008 Page 857 of 1122
R/WC
R/WC
SPC
STA
27
19
11
—
—
R
R
R
R
R
R
0
0
0
3
0
DEV1
BUM
R/W
R/W
26
18
10
—
—
R
R
R
R
R
R
0
0
0
2
0
22. PCI Controller (PCIC)
REJ09B0370-0400
PBBE
DEV0
MES
R/W
R/W
25
17
—
R
R
R
R
R
R
1
0
9
0
1
0
R/WC
R/WC
DPD
SER
R/W
R/W
R/W
R/W
IOS
24
16
—
R
R
0
0
8
0
0
0