HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 61

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.4
4.5
4.6
4.7
Section 5 Exceptions
5.1
5.2
5.3
5.4
5.5
4.3.8
4.3.9
4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced
Instruction Cache (IC)....................................................................................................... 116
4.4.1
4.4.2
4.4.3
Memory-Mapped Cache Configuration (SH7751)............................................................ 120
4.5.1
4.5.2
4.5.3
4.5.4
Memory-Mapped Cache Configuration (SH7751R) ......................................................... 125
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
Store Queues ..................................................................................................................... 131
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
Overview........................................................................................................................... 137
5.1.1
5.1.2
Register Descriptions ........................................................................................................ 138
Exception Handling Functions .......................................................................................... 139
5.3.1
5.3.2
Exception Types and Priorities ......................................................................................... 140
Exception Flow ................................................................................................................. 143
5.5.1
5.5.2
5.5.3
Coherency between Cache and External Memory ............................................... 113
Prefetch Operation ............................................................................................... 113
Mode .................................................................................................................... 114
Configuration ....................................................................................................... 116
Read Operation .................................................................................................... 119
IC Index Mode ..................................................................................................... 120
IC Address Array ................................................................................................. 120
IC Data Array....................................................................................................... 122
OC Address Array................................................................................................ 123
OC Data Array ..................................................................................................... 124
IC Address Array ................................................................................................. 125
IC Data Array....................................................................................................... 127
OC Address Array................................................................................................ 128
OC Data Array ..................................................................................................... 129
Summary of Memory-Mapped OC Addresses..................................................... 130
SQ Configuration ................................................................................................. 131
SQ Writes............................................................................................................. 131
Transfer to External Memory............................................................................... 132
Determination of SQ Access Exception............................................................... 133
SQ Read (SH7751R only).................................................................................... 133
SQ Usage Notes (SH7751 Only).......................................................................... 134
Features................................................................................................................ 137
Register Configuration......................................................................................... 137
Exception Handling Flow .................................................................................... 139
Exception Handling Vector Addresses ................................................................ 139
Exception Flow .................................................................................................... 143
Exception Source Acceptance.............................................................................. 144
Exception Requests and BL Bit ........................................................................... 146
........................................................................................................... 137
Rev.4.00 Oct. 10, 2008 Page lix of xcviii
REJ09B0370-0400