HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 196

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. Memory Management Unit (MMU)
3.7.3
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry
is selected by bits [9:8].
In the data field, SA is indicated by bits [2:0], and TC by bit [3].
The following two kinds of operation can be used on ITLB data array 2:
1. ITLB data array 2 read
2. ITLB data array 2 write
Rev.4.00 Oct. 10, 2008 Page 96 of 1122
REJ09B0370-0400
Legend:
PPN:
V:
E:
SZ:
Address field
SA and TC are read into the data field from the ITLB entry corresponding to the entry set in
the address field.
SA and TC specified in the data field are written to the ITLB entry corresponding to the entry
set in the address field.
Data field
Physical page number
Validity bit
Entry
Page size bits
ITLB Data Array 2
31
31
1 1 1 1 0 0
30 29 28
Figure 3.14 Memory-Mapped ITLB Data Array 1
1 1
24
23
0
PR:
C:
SH:
:
Protection key data
Cacheability bit
Share status bit
Reserved bits (0 write value, undefined read value)
PPN
10 9 8 7
10 9 8 7
E
V
PR
6 5
SZ
4 3
C
2 1 0
SH
0