HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 604
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14. Direct Memory Access Controller (DMAC)
14.2
14.2.1
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a counter feedback function,
and during a DMA transfer they indicate the next source address. In single address mode, the SAR
value is ignored when a device with DACK has been specified as the transfer source.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev.4.00 Oct. 10, 2008 Page 504 of 1122
REJ09B0370-0400
Initial value:
Initial value:
R/W:
R/W:
Register Descriptions
DMA Source Address Registers 0–3 (SAR0–SAR3)
Bit:
Bit:
R/W
R/W
31
23
—
—
R/W
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
30
—
R/W
29
—
R/W
28
—
R/W
27
—
R/W
26
—
R/W
25
—
R/W
R/W
24
—
—
0
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