HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 493

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when
reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0.
13.3
13.3.1
This LSI supports both big-endian mode, in which the most significant byte (MSByte) is at the 0
address end in a string of byte data, and little-endian mode, in which the least significant byte
(LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a power-on
reset by means of the RESET pin, big-endian mode being set if the MD5 pin is low, and little-
endian mode if it is high.
A data bus width of 8, 16, or 32 bits can be selected for normal memory, 16 or 32 bits for DRAM,
32 bit for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data alignment is
carried out according to the data bus width and endian mode of each device. Accordingly, when
the data bus width is narrower than the access size, multiple bus cycles are automatically
generated to reach the access size. In this case, access is performed by automatically incrementing
addresses to the bus width. For example, when a long word access is performed at the area with an
8-bit bus width in the SRAM interface, each address is incremented one by one, and then access is
performed four times. In the 32-byte transfer, a total of 32-byte data is continuously transferred
according to the set bus width. The first access is performed on the data for which there was an
access request, and the remaining accesses are performed in 32-byte boundary data using
waparound. During these transfers, the bus is not released and refresh operation is not performed.
In this LSI, data alignment and data length conversion between the different interfaces is
performed automatically. Quadword access is used only in transfer by the DMAC.
The relationship between the endian mode, device data length, and access unit, is shown in tables
13.8 to 13.13.
RTCSR,
RTCNT,
RTCOR
RFCR
Operation
Endian/Access Size and Data Alignment
15
15
1
1
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
14
14
0
0
13
13
1
1
12
12
0
0
11
11
0
0
10
10
1
1
9
0
9
8
1
8
7
7
Rev.4.00 Oct. 10, 2008 Page 393 of 1122
6
6
Write data
5
5
13. Bus State Controller (BSC)
Write data
4
4
3
3
REJ09B0370-0400
2
2
1
1
0
0