HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 596

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
• When a BREQ signal is input from the external device while DRAM/synchronous DRAM is
Both above phenomena can be avoided by not using the BREQ signal. If the BREQ signal is to be
used, disable refresh operations during normal operation. If refresh operations are required, carry
them out at one time with the BREQEN bit in BCR1 cleared to 0.
Synchronous DRAM Mode Register Settings (SH7751 Only): The following conditions must
be satisfied when setting the synchronous DRAM mode register.
• The DMAC must not be activated until synchronous DRAM mode register setting is
• Register setting for the on-chip peripheral modules*
Notes: 1. If a conflict occurs between synchronous DRAM mode register setting and memory
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set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), assertion of the
BACK signal (low-level) in response to the BREQ signal may be for only one cycle at CKIO.
completed.*
DRAM mode register setting is completed.*
2. This applies to the following on-chip peripheral modules: CPG, RTC, INTC, TMU,
3. If synchronous DRAM mode register setting is performed immediately following write
access using the DMAC, neither operation can be guaranteed.
SCI, SCIF, and H-UDI.
access to the on-chip peripheral modules*
modules cannot be guaranteed. Note that following power-on, synchronous DRAM
mode register settings should be performed before accessing synchronous DRAM.
After making mode register settings, do not change them.
1
3
2
, the values written to the on-chip peripheral
2
must not be performed until synchronous