HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 925

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.1.3
Table 21.1 shows the H-UDI pin configuration.
Table 21.1 H-UDI Pins
Pin Name
Clock pin
Mode pin
Reset pin
Data input
pin
Data output
pin
Emulator pin
Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or
2. When designing a board that enables the use of an emulator, or when using interrupts
Pin Configuration
when using interrupts and resets via the H-UDI, there is no problem in connecting a
pullup resistance externally.
and resets via the H-UDI, drive TRST low for a period overlapping RESET at power-on,
and also provide for control by TRST alone.
Abbreviation I/O
TCK
TMS
TRST
TDI
TDO
ASEBRK/
BRKACK
AUDSYNC
AUDCK
AUDATA3–
AUDATA0
Input
Input
Input
Input
Output The data output pin. Data is sent to the
Input/
output
Output Dedicated emulator pin
Function
Same as the JTAG serial clock input
pin. Data is transferred from data input
pin TDI to the H-UDI circuit, and data is
read from data output pin TDO, in
synchronization with this signal.
The mode select input pin. Changing
this signal in synchronization with TCK
determines the meaning of the data
input from TDI. The protocol conforms
to the JTAG (IEEE Std 1149.1)
specification.
The input pin that resets the H-UDI.
This signal is received asynchronously
with respect to TCK, and effects a reset
of the JTAG interface circuit when low.
TRST must be driven low for a certain
period when powering on, regardless of
whether or not JTAG is used. This
differs from the IEEE specification.
The data input pin. Data is sent to
the H-UDI circuit by changing this
signal in synchronization with TCK.
H-UDI circuit by reading this signal in
synchronization with TCK.
Dedicated emulator pin
21. High-performance User Debug Interface (H-UDI)
Rev.4.00 Oct. 10, 2008 Page 825 of 1122
When Not Used
Open*
Open*
*
Open*
Open
Open*
Open
REJ09B0370-0400
2,
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3
1
1
1
1