HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 350

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9. Power-Down Modes
Table 9.4
Module
Interrupt controller
User break controller
Bus state controller
On-chip oscillation circuits
Timer unit
Realtime clock
Direct memory access controller
Serial communication interface
Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer
The procedure for a transition to standby mode is shown below.
1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT.
2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction.
3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
9.6.2
Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset via the RESET and MRESET pins.
Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI,
IRL *
clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0
pins both go low. Interrupt exception handling is then executed, and the code corresponding to the
interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the
BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack
before executing the SLEEP instruction.
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REJ09B0370-0400
Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to
be used for the up-count in bits CKS2–CKS0 in the WTCSR register.
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
1
, RTC, or GPIO *
results are not guaranteed if standby mode is entered during transfer.
*
Exit from Standby Mode
Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit
(TMU)).
State of Registers in Standby Mode
2
interrupt is detected, the WDT starts counting. After the count overflows,
Initialized Registers
—
—
—
—
TSTR register*
—
—
See Appendix A, Address List See Appendix A, Address List
Registers That Retain
Their Contents
All registers
All registers
All registers
All registers
All registers except TSTR
All registers
All registers