HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 80

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 13.8 Example of 16-Bit Data Width SRAM Connection ............................................... 408
Figure 13.9 Example of 8-Bit Data Width SRAM Connection ................................................. 409
Figure 13.10 SRAM Interface Wait Timing (Software Wait Only) ............................................ 410
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal) .......... 411
Figure 13.12 SRAM Interface Read Strobe Negate Timing (AnS = 1, AnW = 4, and AnH = 2) 412
Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3) ............................... 413
Figure 13.14 Basic DRAM Access Timing ................................................................................. 415
Figure 13.15 DRAM Wait State Timing ..................................................................................... 416
Figure 13.16 DRAM Burst Access Timing ................................................................................. 417
Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)............................ 418
Figure 13.18 Burst Access Timing in DRAM EDO Mode.......................................................... 419
Figure 13.19 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
Figure 13.19 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
Figure 13.19 (3) DRAM Burst Bus Cycle, RAS Down Mode Start
Figure 13.19 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
Figure 13.20 CAS-Before-RAS Refresh Operation..................................................................... 424
Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1).............. 425
Figure 13.22 DRAM Self-Refresh Cycle Timing........................................................................ 426
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .......... 428
Figure 13.24 Basic Timing for Synchronous DRAM Burst Read ............................................... 431
Figure 13.25 Basic Timing for Synchronous DRAM Single Read.............................................. 433
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write .............................................. 434
Figure 13.27 Basic Timing for Synchronous DRAM Single Write............................................. 436
Figure 13.28 Burst Read Timing ................................................................................................. 438
Figure 13.29 Burst Read Timing (RAS Down, Same Row Address).......................................... 439
Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses)................................. 440
Figure 13.31 Burst Write Timing ................................................................................................ 441
Figure 13.32 Burst Write Timing (Same Row Address) ............................................................. 442
Figure 13.33 Burst Write Timing (Different Row Addresses) .................................................... 443
Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding
Figure 13.35 Auto-Refresh Operation ......................................................................................... 448
Figure 13.36 Synchronous DRAM Auto-Refresh Timing........................................................... 448
Figure 13.37 Synchronous DRAM Self-Refresh Timing ............................................................ 450
Figure 13.38 (1) Synchronous DRAM Mode Write Timing (PALL)......................................... 452
Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ............... 453
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Burst Read Cycle.................................................................................................... 446
(Fast Page Mode, RCD = 0, AnW = 0)............................................................ 420
(Fast Page Mode, RCD = 0, AnW = 0)............................................................ 421
(EDO Mode, RCD = 0, AnW = 0)................................................................... 422
(EDO Mode, RCD = 0, AnW = 0)................................................................... 423