HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 31

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Item
13.3.11 Bus Arbitration 490, 491 Description amended
Page
Revision (See Manual for Details)
There are two bus arbitration modes:
slave mode. In master mode the bus is held on a constant
basis, and is released to another device in response to a bus
request. In slave mode the bus is not held on a constant basis;
a bus request is issued each time an external bus cycle occurs,
and the bus is released again at the end of the access.
Master mode and slave mode can be specified by the external
mode pins.
external mode pin settings. In master mode and slave mode,
the bus goes to the high-impedance state when not being held.
description, an external device that issues bus requests is also
referred to as a slave.
To prevent incorrect operation of connected devices when the
bus is transferred between master and slave, all bus control
signals are negated before the bus is released. When
mastership of the bus is received, also, bus control signals
begin driving the bus from the negated state. Since signals are
driven to the same value by the master and slave exchanging
the bus, output buffer collisions can be avoided.
Instead of a slave mode chip. In the following
See Appendix C, Mode Pin Settings, for the
Rev.4.00 Oct. 10, 2008 Page xxix of xcviii
REJ09B0370-0400
master mode, and

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