HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 560

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
13.3.7
In this LSI, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory
space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA
specification version 4.2 (PCMCIA2.1).
Figure 13.44 shows an example of PCMCIA card connection to this LSI. To enable active
insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a
3-state buffer must be connected between this LSI bus interface and the PCMCIA cards.
As operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard, this
LSI supports only little-endian mode setting and the little-endian mode PCMCIA interface.
When the MMU is on, PCMCIA interface can be set in MMU page units, and there is a choice of
8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory,
8-bit I/O space, 16-bit I/O space, or dynamic bus sizing. See section 3, Memory Management Unit
(MMU), for details of the setting method. When the MMU is off, the setting of bits SA2 to SA0 of
PTEA is always used for access.
Rev.4.00 Oct. 10, 2008 Page 460 of 1122
REJ09B0370-0400
CKIO
A25–A5
A4–A0
CSn
RD/WR
RD
D31–D0
(read)
BS
RDY
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
PCMCIA Interface
TS1
T1
Figure 13.43 Burst ROM Wait Access Timing
TB2
TH1
TS1
TB1
TB2
TH1
TS1
TB1
TB2
TH1
TS1
TB1
T2
TH1