HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1043

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DMA Transfer End: The following describes the status on termination of a DMA transfer.
• Normal termination
• Abnormal termination
DMA transfer ends after the set number of bytes has been transferred. In the case of normal
termination, the DMA end status bit (DMAST) of the PCIDCR and the DMA transfer start
control bit (DMASTART) are cleared, and the DMA transfer termination interrupt status bit
(DMAIS) is set.
If the DMA transfer interrupt mask bit (DMAIM) is set to 1, the DMA transfer termination
interrupt is issued.
Note that the DMAIS bit is set even if the DMAIM bit is set to 0. The DMAIS bit is
maintained until it is cleared. Therefore, the DMAIS bit must be cleared before starting the
next DMA transfer.
The DMA transfer may terminate abnormally if an error on the PCI bus is detected during data
transfer or the DMA transfer is forcibly terminated.
⎯ Error in data transfer
⎯ Forced termination of DMA transfer
In the case of an abnormal termination, the DMA termination status bit (DMAST) in the
PCIDCR is set when the cause of that abnormal termination (error detection or forced
termination of DMA transfer) occurs. After the data transfer terminates, the DMA transfer start
control bit (DMASTART) is cleared and the DMA transfer termination interrupt status bit
(DMAIS) is set.
If the DMA transfer interrupt mask bit (DMAIM) is set to 1, the DMA transfer termination
interrupt is issued.
In the event of an abnormal termination, the transferred data is not guaranteed.
Figure 22.6 shows an example of DMA transfer flowchart.
When an error occurs during DMA transfer, the DMA transfer is forcibly terminated on the
channel in which the error occurred. There is no effect on data transfers on other channels.
When the PCIDCR and DMASTOP bits for a channel are set, data transfer on that channel
is forcibly terminated. However, when the DMASTOP bit is set, do not write 1 to the
DMASTRT bit. Also, in control bits other than the DMASTOP bit, write the value at the
time of transfer started.
Rev.4.00 Oct. 10, 2008 Page 943 of 1122
22. PCI Controller (PCIC)
REJ09B0370-0400