HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 480

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the
DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for a period
set by TPC[2:0] and TRAS[2:0] bits after an auto-refresh command is issued.
Note: For setting values and the period during which no command is issued, see 23.3.3, Bus
Bit 12: TRAS2
0
1
Note: TRC (Bits 29 to 27): RAS precharge interval at end of refresh
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
BE
0
1
Note:
Rev.4.00 Oct. 10, 2008 Page 380 of 1122
REJ09B0370-0400
Timing.
*
In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit
bus
EDOMODE
0
1
0
1
Bit 11: TRAS1
0
1
0
1
8/16/32/64-Bit Transfer
Single
Setting prohibited
Single/fast page*
EDO
Bit 10: TRAS0
0
1
0
1
0
1
0
1
RAS/DRAM
Assertion Time
9
2
3
4
5
6
7
8
32-Byte Transfer
Single
Setting prohibited
Fast page
EDO
Command Interval after
Synchronous DRAM
Refresh
4 + TRC
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
(Initial value)