HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1035

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Memory Transfers: This section describes how PIO transfers are used to access memory space.
16MB between H'FD000000 and H'FDFFFFFF of area P4 (H'1D000000 to H'1DFFFFFF in area
7) is allocated as PCI memory address space. This space is used as the least significant 24 bits of
the PCI address. However, in memory transfers, the two low bits of the PCI address are ignored,
and B'00 is output to the PCI bus. The most significant 8 bits (MBR [31:24]) of the memory space
base register (PCIMBR) are used as the most significant bits of the PCI address. These two
addresses are combined to specify a 32-bit PCI address.
To transfer to the memory space, first specify the most significant 8 bits of the PCI address in the
PCIMBR, then access the PCI memory address space. If within the 16MB space, the PCI memory
address space can be consecutively accessed simply by setting the PCIMBR once. If it is necessary
to access an address space over the 16MB, set PCIMBR again.
When performing locked transfers in memory transfer mode, set the PCIMBR memory space lock
specification bit (LOCK). While the LOCK bit is set, the memory space is locked.
Note the following when performing LOCK transfers:
• A LOCK transfer consists of one read transfer and one write transfer. Always start with the
• The minimum resource for which the LOCK is guaranteed is a 16-byte block. However, the
• You cannot access other targets while a target is LOCKed (from the LOCK read until the
read transfer. The system will operate correctly if you start with a write transfer, but the
resource LOCK will not be established. Also, the system will operate correctly if you perform
two LOCK read transfers, but the LOCK will be released at the next LOCK write transfer.
system will operate correctly even if LOCK transfers are made to addresses other than where
the LOCK is established.
LOCK write).
⎯ PIO LOCK access of another target ends normally and transfers on the PCI bus are also
⎯ Unlocked PIO transfer requests invoked between a LOCK read and LOCK write end
⎯ DMA transfers are postponed until the LOCK transfer ends.
generated.
normally, but no transfers are generated on the PCI bus.
Rev.4.00 Oct. 10, 2008 Page 935 of 1122
22. PCI Controller (PCIC)
REJ09B0370-0400