HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 782

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16. Serial Communication Interface with FIFO (SCIF)
16.2.7
Note:
SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating
status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the
receive FIFO register.
SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be
read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified.
SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 12—Number of Parity Errors (PER3–PER0): These bits indicate the number of data
bytes in which a parity error occurred in the receive data stored in SCFRDR2.
After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes
in which a parity error occurred.
If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to
PER0 will be 0.
Bits 11 to 8—Number of Framing Errors (FER3–FER0): These bits indicate the number of
data bytes in which a framing error occurred in the receive data stored in SCFRDR2.
After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in
which a framing error occurred.
If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3
to FER0 will be 0.
Rev.4.00 Oct. 10, 2008 Page 682 of 1122
REJ09B0370-0400
Initial value:
Initial value:
*
R/W:
R/W:
Serial Status Register (SCFSR2)
Bit:
Bit:
Only 0 can be written, to clear the flag.
R/(W)*
PER3
ER
15
R
0
7
0
R/(W)*
TEND
PER2
14
R
0
6
1
R/(W)*
PER1
TDFE
13
R
0
5
1
R/(W)*
PER0
BRK
12
R
0
4
0
FER3
FER
11
R
R
0
3
0
FER2
PER
10
R
R
0
2
0
R/(W)*
FER1
RDF
R
9
0
1
0
R/(W)*
FER0
DR
R
8
0
0
0