LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 107

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
8.4.5
D[31:0] (OUTPUT)
END_SEL
nCS, nRD
A[4:2]
A[x:5]
PIO Burst Reads
In this mode, performance is improved by allowing up to 8 DWORD read cycles back-to-back. PIO
burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read
begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert
between bursts for the period specified in
page
asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram
in
Note: Fresh data is supplied each time A[2] toggles.
The endian select signal (END_SEL) has the same timing characteristics as the upper address lines.
Please refer to
specifications for PIO burst read operations.
Note: PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are
Figure
446. The burst cycle ends when either or both nCS and nRD are de-asserted. They may be
not supported.
8.4.
Figure 8.4 Functional Timing for PIO Burst Read Operation
Section 15.5.5, "PIO Burst Read Cycle Timing," on page 446
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DATASHEET
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107
Table 15.9, “PIO Burst Read Cycle Timing Values,” on
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Revision 1.7 (06-29-10)
for the AC timing
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