LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 47

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
4.3.1
PME_TYPE (bit 6) of
PHY_INTERRUPT_SOURCE_1 register
PHY_INTERRUPT_SOURCE_1 register
PHY_INTERRUPT_SOURCE_2 register
PHY_INTERRUPT_SOURCE_2 register
HMAC_WUCSR register
HMAC_WUCSR register
HMAC_WUCSR register
Denotes a level-triggered "sticky" status bit
PMT_CTRL register
PMT_CTRL register
PMT_CTRL register
PMT_CTRL register
HMAC_WUCSR register
PME_POL (bit 2) of
PME_IND (bit 3) of
PME_EN (bit 1) of
WUEN (bit 2) of
WUFR (bit 6) of
MPEN (bit 1) of
MPR (bit 5) of
Port 1 & 2 PHY Power Management
The Port 1 & 2 PHYs provide independent general power-down and energy-detect power-down modes
which reduce PHY power consumption. General power-down mode provides power savings by
powering down the entire PHY, except the PHY management control interface. General power-down
mode must be manually enabled and disabled as described in
Down," on page
In energy-detect power-down mode, the PHY will resume from power-down when energy is seen on
the cable (typically from link pulses). If the ENERGYON interrupt (INT7) of either PHYs
Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
generate an interrupt. These interrupts are reflected in the
(PHY_INT2) for the Port 2 PHY, and bit 26 (PHY_INT1) for the Port 1 PHY. These interrupts can be
used to trigger the IRQ interrupt output pin, as described in
on page
operation and configuration of the PHY energy-detect power-down mode.
INT7_MASK (bit 7) of
INT7_MASK (bit 7) of
INT7 (bit 7) of
INT7 (bit 7) of
52. Refer to
95.
Figure 4.1 PME and PME_INT Signal Generation
Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 95
PME_INT_EN (bit 17)
PMT_CTRL register
PMT_CTRL register
PMT_CTRL register
ED_EN2 (bit 15) of
of INT_EN register
ED_EN1 (bit 14) of
WOL_EN (bit 9) of
DATASHEET
of INT_STS register
ED_STS1 (bit 16) of
PMT_CTRL register
ED_STS2 (bit 17) of
PMT_CTRL register
PME_INT (bit 17)
PMT_CTRL register
WOL_STS (bit 5) of
47
50ms
is unmasked, then the corresponding PHY will
of IRQ_CFG register
Interrupt Status Register (INT_STS)
IRQ_EN (bit 8)
Other System
Section 5.2.3, "Ethernet PHY Interrupts,"
Interrupts
Section 7.2.9.1, "PHY General Power-
LOGIC
Revision 1.7 (06-29-10)
Buffer Type
Polarity &
for details on the
Logic
Port x PHY
bit 27
IRQ
PME