LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 447

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
15.5.6
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
A[x:2], END_SEL
t
t
csh
asu
don
doff
doh
csl
ah
FIFO_SEL
RX Data FIFO Direct PIO Read Cycle Timing
Please refer to
description of this mode.
nCS, nRD
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle
Read Cycle Time
CS, nRD Assertion Time
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
D[31:0]
ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values
Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing
Section 8.4.6, "RX Data FIFO Direct PIO Reads," on page 108
DESCRIPTION
t
asu
DATASHEET
t
don
t
csdv
447
t
csl
t
cycle
t
doh
MIN
45
32
13
0
0
0
0
t
t
doff
ah
TYP
t
csh
Revision 1.7 (06-29-10)
MAX
30
9
for a functional
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS