LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 309

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
REGISTER #
0482h-07FFh
0802h-080Fh
0464-047Fh
045Ah
045Bh
045Ch
045Dh
045Eh
0455h
0456h
0457h
0458h
0459h
045Fh
0460h
0461h
0462h
0463h
0480h
0481h
0800h
0801h
0810h
0811h
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
MAC_TX_EXCOL_CNT_MII
MAC_RX_UNDSZE_CNT_1
MAC_TX_128_TO_255_CNT_MII
MAC_TX_256_TO_511_CNT_MII
MAC_TX_1024_TO_MAX_CNT_MII
MAC_TX_SNGLECOL_CNT_MII
MAC_TX_65_TO_127_CNT_MII
MAC_TX_512_TO_1023_CNT_MII
MAC_TX_TOTALCOL_CNT_MII
MAC_TX_UNDSZE_CNT_MII
MAC_TX_BRDCST_CNT_MII
MAC_TX_MULCST_CNT_MII
MAC_TX_MULTICOL_CNT_MII
MAC_TX_PKTLEN_CNT_MII
MAC_TX_LATECOL_MII
MAC_RX_64_CNT_1
MAC_RX_CFG_1
MAC_VER_ID_1
MAC_IMR_MII
MAC_IPR_MII
RESERVED
RESERVED
RESERVED
RESERVED
SYMBOL
Switch Port 1 CSRs
DATASHEET
Port 0 MAC Transmit 65 to 127 Byte Count Register,
Section 14.5.2.29
Port 0 MAC Transmit 128 to 255 Byte Count Register,
Section 14.5.2.30
Port 0 MAC Transmit 256 to 511 Byte Count Register,
Section 14.5.2.31
Port 0 MAC Transmit 512 to 1023 Byte Count Register,
Section 14.5.2.32
Port 0 MAC Transmit 1024 to Max Byte Count Register,
Section 14.5.2.33
Port 0 MAC Transmit Undersize Count Register,
Section 14.5.2.34
Reserved for Future Use
Port 0 MAC Transmit Packet Length Count Register,
Section 14.5.2.35
Port 0 MAC Transmit Broadcast Count Register,
Section 14.5.2.36
Port 0 MAC Transmit Multicast Count Register,
Section 14.5.2.37
Port 0 MAC Transmit Late Collision Count Register,
Section 14.5.2.38
Port 0 MAC Transmit Excessive Collision Count Register,
Section 14.5.2.39
Port 0 MAC Transmit Single Collision Count Register,
Section 14.5.2.40
Port 0 MAC Transmit Multiple Collision Count Register,
Section 14.5.2.41
Port 0 MAC Transmit Total Collision Count Register,
Section 14.5.2.42
Reserved for Future Use
Port 0 MAC Interrupt Mask Register,
Port 0 MAC Interrupt Pending Register,
Reserved for Future Use
Port 1 MAC Version ID Register,
Port 1 MAC Receive Configuration Register,
Reserved for Future Use
Port 1 MAC Receive Undersize Count Register,
Section 14.5.2.3
Port 1 MAC Receive 64 Byte Count Register,
309
REGISTER NAME
Section 14.5.2.1
Section 14.5.2.43
Section 14.5.2.44
Revision 1.7 (06-29-10)
Section 14.5.2.2
Section 14.5.2.4