LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 53

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
5.2.6
5.2.7
In order for a Host MAC interrupt event to trigger the external IRQ interrupt pin, the desired Host MAC
interrupt event must be enabled in the
enabled via bit 8 (IRQ_EN) of the
Refer to the
for additional information on bit definitions and Host MAC operation.
Power Management Interrupts
Multiple Power Management Event interrupt sources are provided by the LAN9312. The top-level
PME_INT (bit 17) of the
Management interrupt event occurred in the
The
Power Management conditions. These include energy-detect on the Port 1/2 PHYs, and Wake-On-LAN
(wake-up frame or magic packet) detection by the Host MAC.
In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired
Power Management interrupt event must be enabled in the
(PMT_CTRL)
must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the
(IRQ_CFG).
For additional details on power management, refer to
General Purpose Timer Interrupt
A General Purpose Timer (GPT) interrupt is provided in the top-level
(INT_STS)
Purpose Timer Configuration Register (GPT_CFG)
19 of the
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT
must be enabled via the bit 29 (TIMER_EN) in the
(GPT_CFG), bit 19 of the
enabled via bit 8 (IRQ_EN) of the
For additional details on the General Purpose Timer, refer to
on page
TX Status FIFO Overflow
Receive Watchdog Time-Out
Receiver Error
Transmitter Error
TX Data FIFO Underrun
TX Data FIFO Overrun
TX Data FIFO Available
TX Status FIFO Full
TX Status FIFO Level
RX Dropped Frame
RX Data FIFO Level
RX Status FIFO Full
RX Status FIFO Level
Power Management Control Register (PMT_CTRL)
161.
Interrupt Status Register (INT_STS)
and
Interrupt Status Register (INT_STS) on page 174
(bits 15, 14, and/or 9), bit 17 (PME_INT_EN) of the
Interrupt Enable Register (INT_EN)
Interrupt Enable Register (INT_EN)
Interrupt Status Register (INT_STS)
Interrupt Configuration Register
Interrupt Configuration Register
DATASHEET
Interrupt Enable Register
53
Power Management Control Register
is written with 1.
wraps past zero to FFFFh, and is cleared when bit
(bit 19). This interrupt is issued when the
Section 4.3, "Power Management," on page
General Purpose Timer Configuration Register
provides enabling/disabling and status of all
and
Section 12.1, "General Purpose Timer,"
Power Management Control Register
must be set, and IRQ output must be
Chapter 9, "Host MAC," on page 112
(INT_EN), and IRQ output must be
Interrupt Enable Register (INT_EN)
provides indication that a Power
(IRQ_CFG).
(IRQ_CFG).
Interrupt Configuration Register
Interrupt Status Register
Revision 1.7 (06-29-10)
(PMT_CTRL).
General
46.