LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 149

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10.2.4
10.2.4.1
EEPROM ADDRESS
14 and above
8 - 11
12
13
0
1
2
3
4
5
6
7
EEPROM Loader
The EEPROM Loader interfaces to the I
CSRs (via the Register Access MUX). Only system CSRs at addresses 100h and above are accessible
to the EEPROM Loader (with the addition of the
(PMI_DATA)
A8 respectively).
The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset
(DIGITAL_RST bit in the
command via the
Loader, but only the MAC address is loaded into the Host MAC. Refer to
page 36
The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An
overview of the EEPROM content format is shown in
is discussed in detail in the following sections.
EEPROM Loader Operation
Upon a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the
Register
Register
While the EEPROM Loader is active, the READY bit of the
(HW_CFG)
LAN9312 should be attempted. The operational flow of the EEPROM Loader can be seen in
Figure
10.14.
for additional information on the LAN9312 resets.
(E2P_CMD), the EPC_BUSY bit in the
(RESET_CTL)), or upon the issuance of a RELOAD command via the
and
and
EEPROM Valid Flag
MAC Address Low Word [7:0]
MAC Address Low Word [15:8]
MAC Address Low Word [23:16]
MAC Address Low Word [31:24]
MAC Address High Word [7:0]
MAC Address High Word [15:8]
Configuration Strap Values Valid Flag
Configuration Strap Values
Burst Sequence Valid Flag
Number of Bursts
Burst Data
Power Management Control Register (PMT_CTRL)
PHY Management Interface Access Register (PMI_ACCESS)
Table 10.7 EEPROM Contents Format Overview
EEPROM Command Register
Reset Control Register
DESCRIPTION
DATASHEET
2
C/Microwire EEPROM controller, the PHYs, and to the system
149
EEPROM Command Register (E2P_CMD)
(RESET_CTL)), or upon the issuance of a RELOAD
(E2P_CMD). A soft reset will run the EEPROM
Table
PHY Management Interface Data Register
10.7. Each section of EEPROM contents
Hardware Configuration Register
is cleared and no writes to the
2
1
3
4
5
6
nd
rd
st
th
th
th
See
See
Section 4.2, "Resets," on
Byte on the Network
Byte on the Network
Byte on the Network
Byte on the Network
Byte on the Network
Byte on the Network
"Register Data"
"Register Data"
See
Section 10.2.4.5,
Section 10.2.4.5,
at addresses A4 and
EEPROM Command
Revision 1.7 (06-29-10)
VALUE
Table 10.8
A5h
A5h
A5h
Reset Control
will be set.