LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 186

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.2.2.6
BITS
31:0
RX Dropped Frame Counter (RX_DFC)
This counter is incremented every time a receive frame is dropped by the
Host MAC. RX_DFC is cleared on any read of this register.
Note:
Host MAC RX Dropped Frames Counter Register (RX_DROP)
This register indicates the number of receive frames that have been dropped by the Host MAC.
The interrupt RXDFH_INT (bit 23 of the
(INT_STS)) can be issued when this counter passes through its
halfway point (7FFFFFFFh to 80000000h).
Offset:
0A0h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
186
Interrupt Status Register
Size:
32 bits
TYPE
RC
SMSC LAN9312
00000000h
DEFAULT
Datasheet