LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 261

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.9.3
31:28
24:22
BITS
27
26
25
21
20
RESERVED
Device Ready (READY)
When set, this bit indicates that the LAN9312 is ready to be accessed. Upon
power-up, nRST reset, soft reset, or digital reset, the host processor may
interrogate this field as an indication that the LAN9312 has stabilized and is
fully active.
This bit can cause an interrupt if enabled.
Note:
Note:
AMDIX_EN Strap State Port 2
This bit reflects the state of the auto_mdix_strap_2 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_2
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status
Indication Register
AMDIX_EN Strap State Port 1
This bit reflects the state of the auto_mdix_strap_1 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_1
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status
Indication Register
RESERVED
RESERVED - This bit must be written with 0b for proper operation.
Must Be One (MBO). This bit must be set to ‘1’ for normal device operation.
Hardware Configuration Register (HW_CFG)
This register allows the configuration of various hardware features including TX/RX FIFO sizes, Host
MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings
for FIFO memory allocation can be found in
on page
Note: This register can be polled while the LAN9312 is in the reset or not ready state (READY bit is
With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
This bit is identical to bit 0 of the
Register
cleared).
Offset:
121.
(PMT_CTRL).
(Section
(Section
14.4.2.10).
14.4.2.10).
074h
DESCRIPTION
DATASHEET
Power Management Control
261
Section 9.7.3, "FIFO Memory Allocation Configuration,"
Size:
32 bits
TYPE
R/W
R/W
RO
RO
RO
RO
RO
Revision 1.7 (06-29-10)
Note 14.47
Note 14.48
DEFAULT
0b
0b
0b
-
-