LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 187

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.2.7
BITS
29:8
7:0
31
30
CSR Busy
When a 1 is written into this bit, the read or write operation is performed to
the specified Host MAC CSR. This bit will remain set until the operation is
complete. In the case of a read, this indicates that the host can read valid
data from the
Note:
R/nW
When set, this bit indicates that the host is requesting a read operation.
When clear, the host is performing a write.
0: Host MAC CSR Write Operation
1: Host MAC CSR Read Operation
RESERVED
CSR Address
The 8-bit value in this field selects which Host MAC CSR will be accessed
by the read or write operation. The index of each Host MAC CSR is defined
in
Section 14.3, "Host MAC Control and Status Registers," on page
Host MAC CSR Interface Command Register (MAC_CSR_CMD)
This read-write register is used to control the read and write operations to/from the Host MAC. This
register in used in conjunction with the
indirectly access the Host MAC CSR’s.
Note: The full list of Host MAC CSR’s are described in
The MAC_CSR_CMD and MAC_CSR_DATA registers must not be
modified until this bit is cleared.
Registers," on page
MAC," on page
Offset:
Host MAC CSR Interface Data Register
112.
0A4h
DESCRIPTION
269. For more information on the Host MAC, refer to
DATASHEET
Host MAC CSR Interface Data Register (MAC_CSR_DATA)
187
Size:
(MAC_CSR_DATA).
Section 14.3, "Host MAC Control and Status
32 bits
269.
TYPE
R/W
R/W
R/W
RO
SC
Revision 1.7 (06-29-10)
Chapter 9, "Host
DEFAULT
00h
0b
0b
-
to