LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 274

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.3.3
BITS
31:0
Physical Address [31:0]
This field contains the lower 32-bits (31:0) of the Physical Address of the
Host MAC. The content of this field is undefined until loaded from the
EEPROM at power-on. The host can update the contents of this field after
the initialization process has completed.
Host MAC Address Low Register (HMAC_ADDRL)
This read/write register contains the lower 32-bits of the physical address of the Host MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is
loaded from address 01h of the EEPROM. The most significant byte of this register is loaded from
address 04h of the EEPROM.
of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet
physical address. Please refer to
page 137
Offset:
for more information on the EEPROM Loader.
3h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Section 9.6, "Host MAC Address," on page 119
DATASHEET
Section 10.2, "I2C/Microwire Master EEPROM Controller," on
274
Size:
32 bits
TYPE
details the byte ordering
R/W
SMSC LAN9312
FFFFFFFFh
DEFAULT
Datasheet