LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 54

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
5.2.8
5.2.9
Software Interrupt
A general purpose software interrupt is provided in the top level
and
(INT_STS)
This interrupt provides an easy way for software to generate an interrupt, and is designed for general
software usage.
Device Ready Interrupt
A device ready interrupt is provided in the top-level
Enable Register
indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. Writing a 1 to
this bit in the
In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the
Enable Register (INT_EN)
Interrupt Configuration Register
Interrupt Enable Register
is generated when SW_INT_EN (bit 31) of the
Interrupt Status Register (INT_STS)
(INT_EN). The READY interrupt (bit 30) of the
must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
(INT_EN). The SW_INT interrupt (bit 31) of the
(IRQ_CFG).
DATASHEET
54
will clear it.
Interrupt Status Register (INT_STS)
Interrupt Enable Register (INT_EN)
Interrupt Status Register (INT_STS)
Interrupt Status Register (INT_STS)
Interrupt Status Register
SMSC LAN9312
and
Datasheet
Interrupt
Interrupt
is set.