LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 450

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
15.5.9
SYMBOL
t
cycle
t
t
t
A[2], END_SEL
t
t
t
csh
asu
dsu
csl
ah
dh
FIFO_SEL
nCS, nWR
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to
description of this mode.
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
D[31:0]
Write Cycle Time
nCS, nWER Assertion Time
nCS, nWR De-assertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111
DESCRIPTION
t
asu
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
450
t
csl
t
t
cycle
dsu
MIN
45
32
13
7
0
0
0
t
dh
t
ah
TYP
t
csh
MAX
for a functional
SMSC LAN9312
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS