LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 36

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Chapter 4 Clocking, Resets, and Power Management
Revision 1.7 (06-29-10)
4.1
4.2
The LAN9312 includes a clock module which provides generation of all system clocks as required by
the various sub-modules of the device. The LAN9312 requires a fixed-frequency 25MHz clock source
for use by the internal clock oscillator and PLL. This is typically provided by attaching a 25MHz crystal
to the XI and XO pins as specified in
can be provided by driving the XI input pin with a single-ended 25MHz clock source. If a single-ended
source is selected, the clock input must run continuously for normal device operation. The internal PLL
generates a fixed 200MHz base clock which is used to derive all LAN9312 sub-system clocks.
In addition to the sub-system clocks, the clock module is also responsible for generating the clocks
used for the general purpose timer and free-running clock. Refer to
Timer & Free-Running Clock," on page 161
Note: Crystal specifications are provided in
The LAN9312 provides multiple hardware and software reset sources, which allow varying levels of
the LAN9312 to be reset. All resets can be categorized into three reset types as described in the
following sections:
The LAN9312 supports the use of configuration straps to allow automatic custom configurations of
various LAN9312 parameters. These configuration strap values are set upon de-assertion of all chip-
level resets and can be used to easily set the default parameters of the chip at power-on or pin (nRST)
reset. Refer to
of these straps.
Note: The LAN9312 EEPROM Loader is run upon a power-on reset, nRST pin reset, and digital
Table 4.1
sections for detailed information on each of these reset types.
Clocks
Resets
—Power-On Reset (POR)
—nRST Pin Reset
—Digital Reset (DIGITAL_RST)
—Soft Reset (SRST)
—Port 2 PHY Reset
—Port 1 PHY Reset
—Virtual PHY Reset
Chip-Level Resets
Multi-Module Resets
Single-Module Resets
page
reset. Refer to
summarizes the effect of the various reset sources on the LAN9312. Refer to the following
452.
Section 4.2.4, "Configuration Straps," on page 40
Section 10.2.4, "EEPROM Loader," on page 149
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
Section 15.6, "Clock Circuit," on page
36
for additional details.
Table 15.15, “LAN9312Crystal Specifications,” on
for detailed information on the usage
Chapter 12, "General Purpose
for additional information.
452. Optionally, this clock
SMSC LAN9312
Datasheet