LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 131

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
9.8.7
9.8.8
Transmitter Errors
If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation.
TX Error (TXE) will be asserted under the following conditions:
Stopping and Starting the Transmitter
To halt the transmitter, the host must set the STOP_TX bit in the
(TX_CFG). The transmitter will finish sending the current frame (if there is a frame transmission in
progress). When the transmitter has received the TX status for this frame, it will clear the STOP_TX
and TX_ON bits, and will pulse the TXSTOP_INT in the
Once stopped, the host can optionally clear the TX Status and TX Data FIFOs. The host must re-
enable the transmitter by setting the TX_ON bit. If the there are frames pending in the TX Data FIFO
(i.e., TX Data FIFO was not purged), the transmission will resume with this data.
If the actual packet length count does not match the Packet Length field as defined in the TX
command.
Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX
command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do
not match, the Ethernet controller will assert the Transmitter Error (TXE) flag.
Host overrun of the TX Data FIFO.
Overrun of the TX Status FIFO (unless TXSAO is enabled)
DATASHEET
131
Interrupt Status Register
Transmit Configuration Register
Revision 1.7 (06-29-10)
(INT_STS).