LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 179

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.1.4
31:24
23:16
BITS
15:8
7:0
TX Data Available Level
The value in this field sets the level, in number of 64 Byte blocks, at which
the
TX Data FIFO free space is greater than this value, a
Available Interrupt (TDFA)
(INT_STS).
TX Status Level
The value in this field sets the level, in number of DWORD’s, at which the
TX Status FIFO Level Interrupt (TSFL)
Status FIFO used space is greater than this value, a
Interrupt (TSFL)
(INT_STS).
RESERVED - This field must be written with 00h for proper operation.
RX Status Level
The value in this field sets the level, in number of DWORD’s, at which the
RX Status FIFO Level Interrupt (RSFL)
Status FIFO used space is greater than this value, a
Interrupt (RSFL)
(INT_STS).
FIFO Level Interrupt Register (FIFO_INT)
This read/write register configures the limits where the RX/TX Data and Status FIFO’s will generate
system interrupts.
TX Data FIFO Available Interrupt (TDFA)
Offset:
will be generated in the
will be generated in the
will be generated in the
068h
DESCRIPTION
DATASHEET
will be generated. When the TX
will be generated. When the RX
Interrupt Status Register
Interrupt Status Register
179
will be generated. When the
Size:
Interrupt Status Register
RX Status FIFO Level
TX Status FIFO Level
TX Data FIFO
32 bits
TYPE
R/W
R/W
R/W
R/W
Revision 1.7 (06-29-10)
DEFAULT
48h
00h
00h
00h