LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 307

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.5
REGISTER #
0006h-03FFh
0002h-0003h
0402h-040Fh
0000h
0001h
0004h
0005h
0400h
0401h
0410h
0412h
0413h
0411h
This section details the various LAN9312 switch control and status registers that reside within the
switch fabric. The switch control and status registers allow configuration of each individual switch port,
the switch engine, and buffer manager. Switch fabric related interrupts and resets are also controlled
and monitored via the switch CSRs.
The switch CSRs are not memory mapped. All switch CSRs are accessed indirectly via the
Fabric CSR Interface Command Register
Register
(SWITCH_CSR_DIRECT_DATA)
the switch CSRs must be performed through these registers. Refer to
for additional information.
Note: The flow control settings of the switch ports are configured via the
Table 14.12
registers can be categorized into the following sub-sections:
Switch Fabric Control and Status Registers
Section 14.5.1, "General Switch CSRs," on page 318
Section 14.5.2, "Switch Port 0, Port 1, and Port 2 CSRs," on page 322
Section 14.5.3, "Switch Engine CSRs," on page 366
Section 14.5.4, "Buffer Manager CSRs," on page 410
MAC_RX_UNDSZE_CNT_MII
MAC_RX_128_TO_255_CNT_MII
MAC_RX_65_TO_127_CNT_MII
Table 14.12 Indirectly Accessible Switch Control and Status Registers
1 Manual Flow Control Register
(MANUAL_FC_2), and
located in the system CSR address space.
MAC_RX_64_CNT_MII
MAC_RX_CFG_MII
MAC_VER_ID_MII
(SWITCH_CSR_DATA), and
lists the Switch CSRs and their corresponding addresses in order. The switch fabric
SW_DEV_ID
SW_RESET
RESERVED
RESERVED
RESERVED
SYMBOL
SW_IMR
SW_IPR
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII)
General Switch CSRs
Switch Port 0 CSRs
in the system CSR memory mapped address space. All accesses to
DATASHEET
Switch Device ID Register,
Switch Reset Register,
Reserved for Future Use
Switch Global Interrupt Mask Register,
Switch Global Interrupt Pending Register,
Reserved for Future Use
Port 0 MAC Version ID Register,
Port 0 MAC Receive Configuration Register,
Reserved for Future Use
Port 0 MAC Receive Undersize Count Register,
Section 14.5.2.3
Port 0 MAC Receive 64 Byte Count Register,
Port 0 MAC Receive 65 to 127 Byte Count Register,
Section 14.5.2.5
Port 0 MAC Receive 128 to 255 Byte Count Register,
Section 14.5.2.6
307
(MANUAL_FC_1),
(SWITCH_CSR_CMD),
Switch Fabric CSR Interface Direct Data Register
REGISTER NAME
Section 14.5.1.2
Port 2 Manual Flow Control Register
Section 14.5.1.1
Switch Fabric CSR Interface Data
Section 14.5.2.1
Section 14.2.6, "Switch Fabric"
Switch Fabric
Section 14.5.1.3
Section 14.5.1.4
Revision 1.7 (06-29-10)
Section 14.5.2.2
Section 14.5.2.4
registers:
Switch
Port