LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 134

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
9.9.1.1
9.9.1.2
9.9.2
Receive Data FIFO Fast Forward
The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast
Forward bit (RX_FFWD) in the
instruct the LAN9312 to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers
are automatically incremented to the beginning of the next RX packet.
When performing a fast-forward, there must be at least 4 DWORDs of data in the RX Data FIFO for
the packet being discarded. For cases with less than 4 DWORDs, do not use RX_FFWD. In this case
data must be read from the RX Data FIFO and discarded using standard PIO read operations.
After initiating a fast-forward operation, do not perform any reads of the RX Data FIFO until the
RX_FFWD bit is cleared. Other resources can be accessed during this time (i.e., any registers and/or
the other three FIFO’s). Also note that the RX_FFWD will only fast-forward the RX Data FIFO, not the
RX Status FIFO. After an RX fast-forward operation the RX status must still be read from the RX Status
FIFO.
The receiver does not have to be stopped to perform a fast-forward operation.
Force Receiver Discard (Receiver Dump)
In addition to the Receive data Fast Forward feature, LAN9312 also implements a receiver "dump"
feature. This feature allows the host processor to flush the entire contents of the RX Data and RX
Status FIFOs. When activated, the read and write pointers for the RX Data and Status FIFO’s will be
returned to their reset state. To perform a receiver dump, the LAN9312 receiver must be halted. Once
the receiver stop completion is confirmed, the RX_DUMP bit can be set in the
Register
on stopping the receiver, please refer to
information on the RX_DUMP bit, please refer to
(RX_CFG)," on page
RX Packet Format
The RX status words can be read from the RX Status FIFO port, while the RX data packets can be
read from the RX Data FIFO. RX data packets are formatted in a specific manner before the host can
(RX_CFG). The RX_DUMP bit is cleared when the dump is complete. For more information
180.
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Receive Datapath Control Register
DATASHEET
Section 9.9.4, "Stopping and Starting the
134
Section 14.2.2.1, "Receive Configuration Register
(RX_DP_CTRL), the host can
Receive Configuration
Receiver". For more
SMSC LAN9312
Datasheet