LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 124

no-image

LAN9312-NZW

Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN9312-NZW

Lead Free Status / RoHS Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9312-NZW
Manufacturer:
Standard
Quantity:
143
Part Number:
LAN9312-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
Revision 1.7 (06-29-10)
9.8.1
9.8.2
TX Buffer Format
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN9312 in the handling and processing of the associated Ethernet
packet data buffer. Buffer alignment, segmentation and other packet processing parameters are
included in the command structure. The buffer format is illustrated in
Figure 9.4
data shown in this diagram is actually stored in the TX Data FIFO. This must be taken into account
when calculating the actual TX Data FIFO usage. Please refer to
Data FIFO Usage"
TX Command Format
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command
precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command
‘A’ and TX command ‘B’.
There is a 16-bit Packet Tag in the TX command ‘B’ command word. Packet Tags may, if host software
desires, be unique for each packet (i.e., an incrementing count). The value of the tag will be returned
in the TX status word for the associated packet. The Packet tag can be used by host software to
uniquely identify each status word as it is returned to the host.
shows the TX Buffer as it is written into the LAN9312. It should be noted that not all of the
for a detailed explanation on calculating the actual TX Data FIFO usage.
Host Write
Order
2nd
3rd
Last
1st
Figure 9.4 TX Buffer Format
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
31
Offset + Data DWORD0
Optional offset DWORD0
Optional offset DWORDn
DATASHEET
Optional Pad DWORD0
Optional Pad DWORDn
TX Command 'A'
TX Command 'B'
Last Data & PAD
124
.
.
.
.
.
.
.
.
.
.
.
Section 9.8.5, "Calculating Actual TX
0
Figure
9.4.
SMSC LAN9312
Datasheet

Related parts for LAN9312-NZW