LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 160

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
11.4
11.5
11.6
The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock
related events. A 64-bit comparator is included in this block which compares the 64-bit IEEE 1588 clock
with a 64-bit Clock Target loaded in the
( 1 5 8 8 _ C L O C K _ TA R G E T _ H I )
(1588_CLOCK_TARGET_LO).
When the IEEE 1588 clock equals the Clock Target, a clock event occurs which triggers the following:
Note: Writing the IEEE 1588 clock may cause the interrupt event to occur if the new IEEE 1588 clock
The Clock Target reload function (RELOAD_ADD = 1) allows the host to pre-load the next trigger time.
The add function (RELOAD_ADD = 0), allows for a repeatable event. When the Clock Target overflows,
it will wrap around past 0, as will the 64-bit IEEE 1588 clock. Since the Clock Target and Reload / Add
Registers are 64-bits, they require two 32-bit write cycles, one to each half, before the registers are
affected. The writes may be in any order.
In addition to time stamping PTP packets, the IEEE 1588 clock value can be saved into a set of clock
capture registers based on the GPIO[9:8] inputs. When configured as outputs, GPIO[9:8] can be used
to output a signal based on an IEEE 1588 clock target compare event. Refer to
IEEE 1588 Timestamping," on page 163
stamping functions.
The IEEE 1588 hardware time stamp unit provides multiple interrupt conditions. These include time
stamp indication on the transmitter and receiver side of each port, individual GPIO[9:8] input time
stamp interrupts, and a clock comparison event interrupt. All IEEE 1588 interrupts are located in the
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
respective enable bits. Refer to
(1588_INT_STS_EN)," on page 226
All IEEE 1588 interrupts are ANDed with their individual enables and then ORed, as shown in
Figure
When configured as an input, GPIO[9:8] have the added functionality of clearing the Clock Target
interrupt bit (1588_TIMER_INT) of the
on an active edge. GPIO inputs must be active for greater than 40 nS to be recognized as clear events.
For more information on IEEE 1588 GPIO interrupts, refer to
page
Refer to
interrupts.
IEEE 1588 Clock/Events
IEEE 1588 GPIOs
IEEE 1588 Interrupts
The maskable interrupt 1588_TIMER_INT is set in the
(1588_INT_STS_EN).
The RELOAD_ADD bit in the
the new Clock Target behavior:
–RELOAD_ADD = 1:
–RELOAD_ADD = 0:
163.
11.1, generating the 1588_EVNT bit of the
The new Clock Target is loaded from the 64-bit Reload / Add Registers
Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)
Reload/Add Low-DWORD Register
The Clock Target is incremented by the
(1588_CLOCK_TARGET_RELOAD_LO).
value is set equal to the current Clock Target.
Chapter 5, "System Interrupts," on page 49
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
1588 Configuration Register (1588_CONFIG)
Section 14.2.5.23, "1588 Interrupt Status and Enable Register
DATASHEET
for bit-level definitions of all IEEE 1588 interrupts and enables.
a n d
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
160
(1588_CLOCK_TARGET_RELOAD_LO)).
for information on using GPIO[9:8] for IEEE 1588 time
1 5 8 8
1588 Clock Target Reload/Add Low-DWORD Register
Interrupt Status Register
1588 Clock Target High-DWORD Register
C l o c k
for additional information on the LAN9312
1588 Interrupt Status and Enable Register
Ta r g e t
Section 13.2.2, "GPIO Interrupts," on
and are fully maskable via their
L o w - D W O R D
(INT_STS).
is checked to determine
and
(1588 Clock Target
Section 13.2.1, "GPIO
1588 Clock Target
SMSC LAN9312
R e g i s t e r
Datasheet