LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 197

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.4
14.2.4.1
BITS
31
EEPROM Controller Busy (EPC_BUSY)
When a 1 is written into this bit, the operation specified in the
EPC_COMMAND field of this register is performed at the specified
EEPROM address. This bit will remain set until the selected operation is
complete. In the case of a read, this indicates that the Host can read valid
data from the
E2P_DATA registers should not be modified until this bit is cleared. In the
case where a write is attempted and an EEPROM is not present, the
EPC_BUSY bit remains set until the
(EPC_TIMEOUT)
Note:
EEPROM
This section details the EEPROM related System CSR’s. These registers should only be used if an
EEPROM has been connected to the LAN9312. Refer to chapter
EEPROM Controller," on page 137
of the EEPROM Controller (EPC).
EEPROM Command Register (E2P_CMD)
This read/write register is used to control the read and write operations of the serial EEPROM.
EPC_BUSY is set immediately following power-up, or pin reset, or
DIGITAL_RST reset. This bit is also set following the settings of the
SRST bit in the
the EEPROM Loader has finished loading, the EPC_BUSY bit is
cleared. Refer to chapter
page 149
Offset:
EEPROM Data Register
bit is set. At this time the EPC_BUSY bit is cleared.
for more information.
Hardware Configuration Register
1B4h
DESCRIPTION
Section 10.2.4, "EEPROM Loader," on
EEPROM Controller Timeout
DATASHEET
for additional information on the various modes (I
(E2P_DATA). The E2P_CMD and
197
Size:
(HW_CFG). After
32 bits
Section 10.2, "I2C/Microwire Master
TYPE
R/W
SC
Revision 1.7 (06-29-10)
2
C and Microwire)
DEFAULT
0b