LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 449

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
15.5.8
SYMBOL
t
cycle
t
t
t
t
A[x:2], END_SEL
t
t
csh
asu
dsu
csl
ah
dh
nCS, nWR
PIO Write Cycle Timing
Please refer to
Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR De-assertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
D[31:0]
or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any
order.
Section 8.4.8, "PIO Writes," on page 110
Table 15.12 PIO Write Cycle Timing Values
DESCRIPTION
Figure 15.8 PIO Write Cycle Timing
t
asu
DATASHEET
449
t
csl
t
for a functional description of this mode.
t
cycle
dsu
MIN
45
32
13
0
7
0
0
t
dh
t
ah
TYP
t
csh
Revision 1.7 (06-29-10)
MAX
UNITS
nS
nS
nS
nS
nS
nS
nS