LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 273

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.3.2
31:16
BITS
15:0
RESERVED
Physical Address [47:32]
This field contains the upper 16-bits (47:32) of the Physical Address of the
Host MAC. The content of this field is undefined until loaded from the
EEPROM at power-on. The host can update the contents of this field after
the initialization process has completed.
Host MAC Address High Register (HMAC_ADDRH)
This read/write register contains the upper 16-bits of the physical address of the Host MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is
loaded from address 05h of the EEPROM. The second byte (bits [15:8]) is loaded from address 06h
of the EEPROM.
HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical
address. Please refer to
more information on the EEPROM Loader.
Offset:
Section 9.6, "Host MAC Address," on page 119
Section 10.2, "I2C/Microwire Master EEPROM Controller," on page 137
2h
DESCRIPTION
DATASHEET
273
Size:
32 bits
details the byte ordering of the
TYPE
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
FFFFh
-
for