LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 195

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.3.3
31:28
27:16
15:12
BITS
11:0
RESERVED
GPIO Interrupt Enable[11:0] (GPIO[11:0]_INT_EN)
When set, these bits enable the corresponding GPIO interrupt.
Note:
RESERVED
GPIO Interrupt[11:0] (GPIO[11:0]_INT)
These signals reflect the interrupt status as generated by the GPIOs. These
interrupts are configured through the
Register
Note:
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
This read/write register contains the GPIO interrupt status bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these
interrupt bits are cascaded into bit 12 (GPIO) of the
to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits will
still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt
in this register. Bit 12 (GPIO_EN) of the
for an actual system level interrupt to occur. Refer to
additional information.
The GPIO interrupts must also be enabled via bit 12 (GPIO_EN) of
the
interrupt pin (IRQ) to be asserted.
(GPIO_CFG).
As GPIO interrupts, GPIO inputs are level sensitive and must be
active greater than 40 nS to be recognized as interrupt inputs.
Offset:
Interrupt Enable Register (INT_EN)
1E8h
DESCRIPTION
General Purpose I/O Configuration
DATASHEET
Interrupt Enable Register (INT_EN)
195
in order to cause the
Size:
Interrupt Status Register
Chapter 5, "System Interrupts," on page 49
32 bits
must also be set in order
TYPE
R/WC
R/W
RO
RO
(INT_STS). Writing a 1
Revision 1.7 (06-29-10)
DEFAULT
0h
0h
-
-
for